1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and particularly, to a semiconductor integrated circuit having an improved power source system in the integrated circuit.
2. Description of the Related Art
In a conventional dynamic random access memory (DRAM), it is rather desirable to make an integrated circuit itself generate a predetermined voltage, than to directly use an external power source voltage. This is because application of a single external power source needs to be connected to the integrated circuit even when a plurality of voltage levels are required in the integrated circuit.
A conventional DRAM adopts a method of using a single externally applied power source voltage and of generating any other necessary voltages in the integrated circuit. An internal voltage generator is, for example, a substrate potential generator supplying a substrate potential and a well potential, an internal power source voltage generator used as an internal power source, or a reference potential generator used as an internal reference potential.
A voltage generator used as an internal power source is, for example, a boost circuit, a voltage regulator, or the like. These internal voltage generators are used to improve operating margins of an integrated circuit and to ensure its reliability. Particularly, in recent years, an externally applied power source voltage has decreased, and a DRAM mounting boost circuit has been proposed.
FIGS. 1 to 4 are block diagrams respectively showing structural examples of conventional DRAMs. FIG. 1 shows an example where an internal power source voltage generator is not used and a boot strap circuit is used to drive word lines, while an externally applied power source voltage is directly used for peripheral circuits. This method has been adopted in a 1M-bit DRAM or a 4M-bit DRAM, for example.
FIG. 2 shows a method of using an output of an internal voltage regulator which generates a potential obtained by regulating an externally applied power source voltage VCC. This method has been adopted in a 16M-bit DRAM, for example.
Examples shown in FIGS. 3 and 4 do not adopt the boot strap method stated above, but adopt a method of using an output of an internal boosting circuit which generates a potential obtained by boosting an externally applied power source voltage VCC, as a power source for a word line drive circuit, in order to conform to application of an externally applied power source voltage VCC having a lowered voltage. In these examples, FIG. 3 shows a structure in which an externally applied power source voltage VCC is directly used as a power source for peripheral circuits, while FIG. 4 shows a structure using an internal voltage regulator as a power source for peripheral circuits. These methods have been designed and developed for use in a 64M-bit DRAM.
As explained above, conventional techniques teach use of a voltage regulator which generates a voltage lower than an externally applied power source voltage as a power source for peripheral circuits of a DRAM, or use of a boost circuit which generates a voltage higher than an externally applied power source voltage as a power source for word line drive circuits.
However, in a conventional internal power source voltage system, an internal boost circuit is driven by an externally applied power source voltage VCC, thereby boosting the voltage VCC to an internal boost potential .phi.P as shown in FIG. 5. Likewise, an internal voltage regulator reduces an inputted potential VCC to an internal regulated potential .phi.D. In this structure, when the potential level of the voltage VCC changes, the potential levels of the internal boost potential .phi.P and the internal regulated potential .phi.D are changed together.
In a DRAM of a generation which attained only low integration and a relatively low operating speed, changes in the potential levels as stated above fall within an allowable tolerance range. Once having taken into consideration 64M-bit, 256M-bit, and 1 G-bit DRAMs which will attain very large scale integration in the future, even slight changes in potential levels will be enough to cause erroneous operations.
The present invention has been made in view of the above situation, and has an object of providing a semiconductor integrated circuit device which is capable of restricting changes in internal power source potentials even when an externally applied power source potentials changes.